We are a group of five norwegian radio amateurs who started to develop an SDR intended for amateur radio applications in 2004. The main project goals defined are:
- To have an SDR platform for developemt and implementation of analog and digital amateur band modes
- To learn SDR technology and digital signal processing
- To use SDR in amateur radio applications where high performance is needed
A prototype hardware and a software test application with SSB, FM and AM demodulators are developed. PSK31 demodulator is in development. Testing with defined signals from generators and real life tests with signals from antennas is now in progress.
Figure 1 shows the SDRham hardware functional block diagram with two hardware modules, ADC and RSP.
The RF signal from the antenna is sampled after filtering and amplification with a high speed analog to digital converter (ADC) AD6645 from Analog Devices. The sample rate is 64M samples per second. The receive signal processor (RSP) is the Analog Devices AD6620, and it performs digital mixing of the RF signal to base band, decimation of the sample rate and digital filtering. The samples from the RSP are transferred to a PC via USB. A Cypress USB FX2 supports USB communication. The main signal processing is performed on the PC.
Figure 2 shows the SDRham hardware modules, ADC and RSP. The ADC module is KD7O design, see reference. The RSP module is developed in the SDRham project.
Figure 2: SDRham modules ADC and RSP
Figure 3 shows the SDRham test application user interface. The left window shows signals in the time or the frequency domain. The right window is intended to display text from data modes as PSK31.
The test application is written in C++. Most of the signal processing routines are written in assembly to reduce execution time and to utilise the SSE instructions in the Pentium processor.
Figure 4 shows the SDRham signal processing software, where the colour of the blocks indicates the instruction units of the Pentium processor used. GPR is the general purpose register unit , x87 is the math floating point one and SSE is multimedia instruction unit.
In-phase and quadrature (I and Q) samples are received from the hardware via the USB connection. The I- and Q-samples are 24 bit, an I- and Q-sample pair is 48 bit. The samples received are in Two's Complement Big-Endian format. The samples are first converted to Little-Endian format used by the Pentium processor. The samples are then converted to floating point and scaled so that maximum amplitude is one. The scaled floating point samples are processed by the different demodulators depending of mode selected by user.
KD7O, James Scarlett. A High Performance Digital Transceiver Design. QEX Jul/Aug 2002
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